The present invention relates to a Flash EEPROM with an integrated device for limiting the erase source voltage.
It is known that the distinctive feature of Flash EEPROMs over other non-volatile semiconductor memories is the possibility to electrically erase large groups of memory cells simultaneously.
A Flash EEPROM memory cell is a floating-gate MOSFET having an N type source region and an N type drain region formed in a spaced-apart condition in a P type semiconductor layer. The portion of the P type layer between the source and drain regions forms a channel region, and a polysilicon floating gate is placed above the channel region with the interposition of a gate oxide layer. A polysilicon control gate is insulatively disposed over the floating gate. The groups of memory cells which are to be simultaneously erased have the source electrodes commonly connected to a common source line.
In dual power supply Flash EEPROMs, requiring a first external power supply typically of 5 V+/xe2x88x9210% and a second external power supply of approximately 12 V+/xe2x88x9210%, erasure of the memory cells is carried out by applying a high positive voltage to the common source line of the group of memory cells that must be erased, while keeping the control gate electrodes grounded and the drain electrodes floating. In this way, The Fowler-Nordheim tunneling theory occurs, wherein a strong electric field develops in the gate oxide layer causing electrons trapped in the floating gate to tunnel into the source region through the gate oxide layer.
The high electric fields at the surface of the source regions and at the junction between the source regions and the P type layer give rise to hot carrier generation and to large source-to-substrate currents, leakage currents, which are several order of magnitude higher than the Fowler-Nordheim tunneling current.
To control the source-to-substrate currents and the generation of hot carriers, a resistive feedback is normally provided between the 12 V external power supply and the common source line of the group of memory cells that must be erased. Such a resistive feedback is for example the resistivity of a switching transistor provided in series to the common source line to allow switching of the common source line potential between ground, in READ and PROGRAM mode, and the 12 V power supply, in ERASE mode. The actual voltage of the common source line thus depends on the voltage drop across the resistive feedback, the latter depending in turn on the source-to-substrate current, the Fowler-Nordheim current is negligible.
The source-to-substrate current is maximum at the beginning of erasing, when the potential of the floating gate is more negative due to the electrons trapped therein. As erasing proceeds, electrons are extracted from the floating gate and the potential of the latter becomes less negative. The electric fields at the surface of the source regions and at the junction between the source regions and the P type layer decreases, and so does the source-to-substrate current. The voltage drop across the resistive feedback decreases, and the potential of the common source line increases towards 12 V.
In the final phases of erasing, the potential of the common source line of the source regions of the memory cells become unnecessarily high, and this causes the memory cells, especially those that have a low erasing time to be submitted to electric stresses that reduce the memory cell reliability.
In view of the state of the art described, it is an object of the present invention to provide a Flash EEPROM having a device suitable to limit the potential of the source regions of the memory cells during erase, without negatively affecting the reliability of the memory cells.
According to the present invention, such object is achieved by a Flash EEPROM having an array of memory cells which include a common source line connecting together the source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The positive potential and the common source line include a voltage limiting device coupled to the common source line for limiting the potential of the common source line to a prescribed maximum value lower than said positive potential.
Thanks to the present invention, it is possible to limit the source potential of the memory cells in the final phases of erasing, to reduce the electric stresses to which the memory cells are submitted. This increases the memory cells"" reliability.
The voltage limiting device can be embodied by a simple junction diode with cathode coupled to the common source line and anode coupled to a ground potential: in this way, when the potential of the common source line reaches the breakdown voltage of the diode, the latter clamps the potential of the common source line preventing any further increase. If the breakdown voltage of the junction diode is too low, a plurality of serially connected diodes can be provided: in this way, the potential of the common source line is clamped to a voltage equal to the sum of the breakdown voltages of the diodes of the plurality.
In an alternative embodiment, the voltage limiting device can be a bipolar junction transistor, with the emitter coupled to the common source line, collector coupled to ground, and base floating. The potential of the common source line is clamped to a voltage equal to the turn-on voltage of the bipolar junction transistor.